A typical single-junction photovoltaic cell is comprised of a substrate on which to form the device, two ohmic contacts to conduct current to an external electrical circuit, and two or more semiconductor layers in series to form the semiconductor junction. At least one of these semiconductor layers (the absorber) is chosen so that its bandgap is of a value for near optimum conversion of solar radiation. In the typical design, one semiconductor layer is doped n-type, and the adjacent layer is doped p-type. The intimate proximity of these layers forms a semiconductor p-n junction. The p-n junction provides an electric field that facilitates charge separation in the absorber layer(s) when the cell is illuminated, and charge collection at the ohmic contacts.
In the standard photovoltaic cell including the substrate for mounting the cell and two ohmic contacts for conducting current to an external electrical circuit, in addition to the n-type layer and the p-type layer of a two layer semiconductor cell, a three layer cell typically includes an intrinsic (i-type) layer disposed between the n-type layer and the p-type layer for absorption of light.
In the photovoltaic cell, the semiconductor layers may be formed from single crystalline materials, amorphous materials, or polycrystalline materials. However, single crystalline materials are preferred from an efficiency perspective, because efficiencies are available in excess of about 20% in specific single crystalline photovoltaic cells. Nevertheless, the disadvantage associated with single crystalline materials is the high cost of the material as well as the difficulty in depositing the single crystalline materials.
On the other hand, in the case of amorphous materials, one must contend with low carrier mobility, low minority carrier life time, low efficiency, and issues of cell stability. Therefore, while single-crystalline and amorphous materials are utilized in some photovoltaic device applications, semiconductor layers composed of polycrystalline materials are viewed as the preferred alternative for the production of photovoltaic devices that would be economically viable for a wide range of applications.
Polycrystalline materials offer numerous advantages for the production of the photovoltaic cells. However, there is a desire in the industry of the field of polycrystalline materials to increase the efficiency of the polycrystalline photovoltaic cells from the current efficiencies of about 5-10% range to about a range of about 10-15%, and ultimately to advance the efficiencies of polycrystalline photovoltaic cells closer to the 15-25% range of the single crystalline materials.
Cadmium telluride is a semiconductor with electrical properties recognized in the industry as well suited for conversion of sunlight into electrical energy. The material has a bandgap that is nearly optimum for conversion of terrestrial solar radiation and the ability to be doped n-type and p-type, that permits the formation of a large range of junction structures.
One significant technological problem with CdTe-based devices is that it is difficult to form an ohmic contact to the p-type form of the material. This is observed for both single crystalline and polycrystalline p-type CdTe, and results from a combination of large semiconductor work function, and the inability of CdTe to sustain sufficiently high p-type carrier concentration to enable quantum-mechanical tunneling of charge carriers at the CdTe/metal contact interface. In addition to these fundamental problems, the polycrystalline p-type CdTe material used as the absorber in a CdS/CdTe photovoltaic device is typically treated with Cl-containing liquids or vapors just prior to the formation of ohmic contact. The Cl treatments improve junction performance, but also can produce a CdTe surface that is rich in Cl. Furthermore, the formation of oxide layers from atmospheric oxygen or other processes can alter the chemical properties of the p-type CdTe surface. These factors can effect the electrical transport at the contact interface, and alter the characteristics of the ohmic contact.
To remove the contaminated outer surface of the p-type CdTe, wet chemical treatments are often used. In addition to removing unwanted contamination from the surface, these treatments often have the added benefit of forming a Te-rich layer at the surface, and this Te-layer assists in forming the ohmic contact.
Accordingly, there is a need in the art of preparing the back surface of CdS/CdTe thin-film photovoltaic devices, to minimize and/or eliminate the effect of variations and provide uniform reproduceable surfaces onto which subsequent contact layers can be applied--by first utilizing a "dry process" which is inherently compatible with in-line manufacturing and does not produce significant waste products.
U.S. Pat. No. 4,319,069 discloses chemical treatment of a p-CdTe surface prior to contacting to improve the contact characteristics. HNO.sub.3 (oxidizing acid) plus H.sub.3 PO.sub.4 (leveling agent) is employed to form the Te layer. In this patent, the use of .about.5% HNO.sub.3 +H.sub.3 PO.sub.4 chemical pretreatment is used to improve the contact characteristics, and is a subtractive process.
Chemical treatment of a p-CdTe surface prior to contacting to improve the contact characteristics, by use of an oxidizing acid plus a reducing agent (hydrazine or metal alkalide) is disclosed in U.S. Pat. No. 4,456,630. The use of the chemical pretreatment to improve contact characteristics is subtractive processing, and in such a process, generally, there is very limited control over characteristics such as removal rate, selective grain-boundary etching, and thickness of the resulting Te-layer formation.
U.S. Pat. No. 4,766,084 discloses a process for producing an electric contact on a HgCdTe substrate having a p conductivity and application to the production of an N/P diode, and specifically uses ion bombardment for removal etching of the SiO.sub.2 insulator layer.
A process for replacement of chemical etching with a process involving CF.sub.4 plasma etching plus heat treatment to form an improved gate area in n-type .alpha.-Si on top of intrinsic .alpha.-Si is disclosed in U.S. Pat. No. 4,581,099.